The invention relates generally to semiconductor device fabrication and, in particular, to device structures with improved soft error rate suppression and with integrated strain for enhanced performance, and methods for forming such device structures.
The semiconductor industry has embraced strained silicon as an inexpensive and effective way to improve device performance and conserve power of field effect transistors and other bulk device structures fabricated by complementary metal oxide semiconductor (CMOS) processes. In particular, applying mechanical stress to the channel region of a field effect transistor can modify carrier mobility. One conventional approach is to introduce so-called embedded stressors directly into the device structure that are capable of straining the crystal lattice of the channel region. For example, embedded stressors composed of a silicon-germanium material may be formed directly beneath the source and drain regions of a field effect transistor. The lattice constant of the silicon-germanium material is relatively large in comparison with silicon, which delivers compressive strain to the intervening channel region of the field effect transistor.
Typically, the germanium content in these embedded stressors is limited to a maximum of fifteen atomic percent or less. Increasing the germanium content above this level begins to introduce defects and cause strain relaxation. Furthermore, thermal heat treatments during the device fabrication process also tend to relax the strain imparted by embedded stressors. Consequently, these and other limitations ultimately restrict the utility of embedded silicon-germanium stressors for altering the carrier mobility in bulk CMOS field effect transistors.
Designing bulk CMOS field effect transistors with a high tolerance to latch-up caused by high-energy ionizing radiation has increased in importance for high performance integrated circuits used in space applications, as well as those used in terrestrial environments for military and other high-reliability applications. Impinging high-energy ionizing radiation (e.g., cosmic ray, neutron, proton, alpha) generates electron-hole pairs by ionization of atoms of the host material along its track, which induces latch-up and single event upsets. Because the integrated circuit cannot be easily replaced in space applications, chip failure induced by bulk CMOS devices susceptible to latch-up may prove catastrophic.
Conventionally, a blanket buried recombination layer has been used for the purpose of radiation hardening. The continuous blanket recombination layer reduces charge collection from an event precipitated by ionization radiation, such as cosmic rays, which reduces device sensitivity to latchup and also to single event upsets. However, blanket buried recombination layers potentially damage the channel region of field effect transistors, which may dramatically degrade device performance.
In summary, improved device structures and fabrication methods are needed for bulk CMOS devices, such as field effect transistors, that overcome these and other deficiencies of conventional device structures and fabrication methods by permitting simultaneous improvements in the strain imparted to the device structure and soft error rate suppression.